Implementation Challenges in FFNN Architecture Design for PQ Analysis on FPGA

The present study addresses the implementation challenges in Feedforward neural network (FFNN) architecture design using the most efficient resources. Power quality (PQ) issues are a major concern in the present day. FPGAs (Field programmable gate arrays) are essential in PQ analysis, particularly in smart meters for data processing, storage, and transmission. Artificial neural networks are selected for PQ event classification as they are found to be more robust once they are trained with a large number of data sets. FPGA's reconfigurability, which makes use of abundant hardware resources to create intricate and time-sensitive data processing units, is one of its greatest features. Due to data loss in the data channel unit caused by the FPGA architecture's support for fixed point arithmetic, the PQ event detection module and classification model must be realized with greater accuracy than software implementation approaches. Most of the work reported, with FFNN (Feedforward neural network) structure occupying a large number of multipliers and adders for classification, most of the work reported has not addressed to minimize the data path resources for FFNN instead have addressed in improving classification accuracy. Based on these issues, this paper addresses the implementation challenges in FFNN architecture design by proposing improved and fast architectures. The proposed FFNN architecture design uses optimum resources. The FFNN-based classifier is designed to perform PQ event detection and classification with 99.5% accuracy. The FFNN processor operates at the maximum frequency of 238 MHz. The present paper addresses the hardware implementation of FFNN cores on the FPGA platform. Interfacing FFNN with all other glue logic modules will require FIFO architecture and a data synchronization network. The proposed designs for FFNN can be used as IP cores for any signal and control applications.